The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, manufacturing and testing processes become more difficult.
A wide variety of techniques have been used in electronic circuits and devices to ensure that, once they are manufactured, they operate fully in compliance with their intended design and implementation specifications. Many of the more complex circuit designs include circuits that permit in-circuit testing via circuit access pins. The IEEE 1149.1 JTAG recommendation, for example, provides test circuit architecture for use inside such circuits. This architecture includes a test access port (TAP) controller coupled to the circuit pins for providing access to and for controlling various standard features designed into such circuits. Some of these features are internal scan, boundary scan, built-in test and emulation.
For a variety of implementations, different circuit paths are tested using the JTAG recommendation, depending upon the type of test being performed. Mechanical connections (i.e., jumpers) have typically been used to select such a desired circuit path for JTAG-type testing. Setting mechanical connections, however, typically requires access to the connections being set. For example, circuit modules (e.g., permanent and/or reusable blocks and integrated circuits (ICs)) can be stacked on top of one another, such that in setting jumpers the circuit modules muist be pulled apart. If mistakes are made in setting the jumpers, the process of pulling apart the modules and setting the jumpers must be repeated. The implementation of this mechanical connection-setting, approach has been challenging. For example, taking apart modules for making connections involves a risk of damaging the connectors, boards and/or other circuitry involved therewith.
Current JTAG and other circuit testing approaches have typically been limited to the testing of powered circuits. For instance, typical diagnostic testing involves the passage of test signals after power-up of the circuit being tested, with the test signals passing through circuits during the operation thereof. Therefore, JTAG and other circuit testing approaches typically have not been used for testing circuits prior to power-up.
In addition, for many chip designs, customized chips are made by describing their functionality using a hardware-description language (HDL), such as Verilog or VHDL. The hardware description is often written to characterize the design in terms of a set of functional macros. The design is computer simulated to ensure that the custom design criteria are satisfied. For highly-complex custom chip designs, the above process can be burdensome and costly. The highly integrated structure of such chips leads to unexpected problems, such as signal timing, noise-coupling and signal-level issues. Consequently, such complex custom chip designs involve extensive validation. This validation is generally performed at different stages using a Verilog or VHDL simulator. Once validated at this level, the Verilog or VHDL HDL code is synthesized, for example, using “Synopsis,” to a netlist that is supplied to an ASIC (Application Specific Integrated Circuit) foundry for prototype fabrication. The ASIC prototype is then tested in silicon. Even after such validation with the Verilog or VHDL simulator, unexpected problems are typical. Overcoming these problems involves more iterations of the above process, with testing and validation at both the simulation and prototype stages. Such repetition significantly increases the design time and cost to such a degree that this practice is often intolerable in today's time-sensitive market.
These and other difficulties present challenges to the design and testing for a variety of applications.